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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ICC_CTLR, Interrupt Controller Control Register</h1><p>The ICC_CTLR characteristics are:</p><h2>Purpose</h2>
        <p>Controls aspects of the behavior of the GIC CPU interface and provides information about the features implemented.</p>
      <h2>Configuration</h2><p>This register is banked between ICC_CTLR and ICC_CTLR_S and ICC_CTLR_NS.<br/></p><p>AArch32 System register ICC_CTLR bits [31:0] (ICC_CTLR_S) are architecturally mapped to AArch64 System register <a href="AArch64-icc_ctlr_el1.html">ICC_CTLR_EL1[31:0]</a> (ICC_CTLR_EL1_S).</p><p>AArch32 System register ICC_CTLR bits [31:0] (ICC_CTLR_NS) are architecturally mapped to AArch64 System register <a href="AArch64-icc_ctlr_el1.html">ICC_CTLR_EL1[31:0]</a> (ICC_CTLR_EL1_NS).</p><p>This register is present only when EL1 is capable of using AArch32 and FEAT_GICv3 is implemented. Otherwise, direct accesses to ICC_CTLR are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>ICC_CTLR is a 32-bit register.</p>

      
        <p>This register has the following instances:</p>

      
        <ul>
<li>ICC_CTLR, when EL3 is not implemented
</li><li>ICC_CTLR_S, when EL3 is implemented
</li><li>ICC_CTLR_NS, when EL3 is implemented
</li></ul>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="12"><a href="#fieldset_0-31_20">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-19_19">ExtRange</a></td><td class="lr" colspan="1"><a href="#fieldset_0-18_18">RSS</a></td><td class="lr" colspan="2"><a href="#fieldset_0-17_16">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15">A3V</a></td><td class="lr" colspan="1"><a href="#fieldset_0-14_14">SEIS</a></td><td class="lr" colspan="3"><a href="#fieldset_0-13_11">IDbits</a></td><td class="lr" colspan="3"><a href="#fieldset_0-10_8">PRIbits</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_7">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-6_6">PMHE</a></td><td class="lr" colspan="4"><a href="#fieldset_0-5_2">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1">EOImode</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">CBPR</a></td></tr></tbody></table><h4 id="fieldset_0-31_20">Bits [31:20]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-19_19">ExtRange, bit [19]</h4><div class="field">
      <p>Extended INTID range (read-only).</p>
    <table class="valuetable"><tr><th>ExtRange</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>CPU interface does not support INTIDs in the range 1024..8191.</p>
<p>Behavior is <span class="arm-defined-word">UNPREDICTABLE</span> if the IRI delivers an interrupt in the range 1024 to 8191 to the CPU interface.</p>
<div class="note"><span class="note-header">Note</span><p>Arm strongly recommends that the IRI is not configured to deliver interrupts in this range to a PE that does not support them.</p></div></td></tr><tr><td class="bitfield">0b1</td><td><p>CPU interface supports INTIDs in the range 1024..8191.</p>
<p>All INTIDs in the range 1024..8191 are treated as requiring deactivation.</p></td></tr></table>
      <p>If EL3 is implemented, ICC_CTLR_EL1.ExtRange is an alias of <a href="AArch64-icc_ctlr_el3.html">ICC_CTLR_EL3</a>.ExtRange.</p>
    </div><h4 id="fieldset_0-18_18">RSS, bit [18]</h4><div class="field">
      <p>Range Selector Support. Possible values are:</p>
    <table class="valuetable"><tr><th>RSS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Targeted SGIs with affinity level 0 values of 0 - 15 are supported.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Targeted SGIs with affinity level 0 values of 0 - 255 are supported.</p>
        </td></tr></table>
      <p>This bit is read-only.</p>
    </div><h4 id="fieldset_0-17_16">Bits [17:16]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-15_15">A3V, bit [15]</h4><div class="field">
      <p>Affinity 3 Valid. Read-only and writes are ignored. Possible values are:</p>
    <table class="valuetable"><tr><th>A3V</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The CPU interface logic supports nonzero values of Affinity 3 in SGI generation System registers.</p>
        </td></tr></table><p>If EL3 is implemented and using AArch32, this bit is an alias of <a href="AArch32-icc_mctlr.html">ICC_MCTLR</a>.A3V.</p>
<p>If EL3 is implemented and using AArch64, this bit is an alias of <a href="AArch64-icc_ctlr_el3.html">ICC_CTLR_EL3</a>.A3V.</p></div><h4 id="fieldset_0-14_14">SEIS, bit [14]</h4><div class="field">
      <p>SEI Support. Read-only and writes are ignored. Indicates whether the CPU interface supports local generation of SEIs:</p>
    <table class="valuetable"><tr><th>SEIS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The CPU interface logic does not support local generation of SEIs.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The CPU interface logic supports local generation of SEIs.</p>
        </td></tr></table><p>If EL3 is implemented and using AArch32, this bit is an alias of <a href="AArch32-icc_mctlr.html">ICC_MCTLR</a>.SEIS.</p>
<p>If EL3 is implemented and using AArch64, this bit is an alias of <a href="AArch64-icc_ctlr_el3.html">ICC_CTLR_EL3</a>.SEIS.</p></div><h4 id="fieldset_0-13_11">IDbits, bits [13:11]</h4><div class="field">
      <p>Identifier bits. Read-only and writes are ignored. The number of physical interrupt identifier bits supported:</p>
    <table class="valuetable"><tr><th>IDbits</th><th>Meaning</th></tr><tr><td class="bitfield">0b000</td><td>
          <p>16 bits.</p>
        </td></tr><tr><td class="bitfield">0b001</td><td>
          <p>24 bits.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>If EL3 is implemented and using AArch32, this field is an alias of <a href="AArch32-icc_mctlr.html">ICC_MCTLR</a>.IDbits.</p>
<p>If EL3 is implemented and using AArch64, this field is an alias of <a href="AArch64-icc_ctlr_el3.html">ICC_CTLR_EL3</a>.IDbits.</p></div><h4 id="fieldset_0-10_8">PRIbits, bits [10:8]</h4><div class="field"><p>Priority bits. Read-only and writes are ignored. The number of priority bits implemented, minus one.</p>
<p>An implementation that supports two Security states must implement at least 32 levels of physical priority (5 priority bits).</p>
<p>An implementation that supports only a single Security state must implement at least 16 levels of physical priority (4 priority bits).</p>
<div class="note"><span class="note-header">Note</span><p>This field always returns the number of priority bits implemented, regardless of the Security state of the access or the value of <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS.</p></div><p>The division between group priority and subpriority is defined in the binary point registers <a href="AArch32-icc_bpr0.html">ICC_BPR0</a> and <a href="AArch32-icc_bpr1.html">ICC_BPR1</a>.</p>
<p>If EL3 is implemented and using AArch32, physical accesses return the value from <a href="AArch32-icc_mctlr.html">ICC_MCTLR</a>.PRIbits.</p>
<p>If EL3 is implemented and using AArch64, physical accesses return the value from <a href="AArch64-icc_ctlr_el3.html">ICC_CTLR_EL3</a>.PRIbits.</p>
<p>If EL3 is not implemented, physical accesses return the value from this field.</p></div><h4 id="fieldset_0-7_7">Bit [7]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-6_6">PMHE, bit [6]</h4><div class="field">
      <p>Priority Mask Hint Enable. Controls whether the priority mask register is used as a hint for interrupt distribution:</p>
    <table class="valuetable"><tr><th>PMHE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Disables use of <a href="AArch32-icc_pmr.html">ICC_PMR</a> as a hint for interrupt distribution.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Enables use of <a href="AArch32-icc_pmr.html">ICC_PMR</a> as a hint for interrupt distribution.</p>
        </td></tr></table><p>If EL3 is implemented:</p>
<ul>
<li>If EL3 is using AArch32, this bit is an alias of <a href="AArch32-icc_mctlr.html">ICC_MCTLR</a>.PMHE.
</li><li>If EL3 is using AArch64, this bit is an alias of <a href="AArch64-icc_ctlr_el3.html">ICC_CTLR_EL3</a>.PMHE.
</li><li>If <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS == 0, this bit is read-only.
</li><li>If <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS == 1, this bit is read/write.
</li></ul>
<p>If EL3 is not implemented, it is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether this bit is read-only or read/write:</p>
<ul>
<li>If this bit is read-only, an implementation can choose to make this field RAZ/WI or RAO/WI.
</li><li>If this bit is read/write, it resets to zero.
</li></ul></div><h4 id="fieldset_0-5_2">Bits [5:2]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-1_1">EOImode, bit [1]</h4><div class="field">
      <p>EOI mode for the current Security state. Controls whether a write to an End of Interrupt register also deactivates the interrupt:</p>
    <table class="valuetable"><tr><th>EOImode</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="AArch32-icc_eoir0.html">ICC_EOIR0</a> and <a href="AArch32-icc_eoir1.html">ICC_EOIR1</a> provide both priority drop and interrupt deactivation functionality. Accesses to <a href="AArch32-icc_dir.html">ICC_DIR</a> are <span class="arm-defined-word">UNPREDICTABLE</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="AArch32-icc_eoir0.html">ICC_EOIR0</a> and <a href="AArch32-icc_eoir1.html">ICC_EOIR1</a> provide priority drop functionality only. <a href="AArch32-icc_dir.html">ICC_DIR</a> provides interrupt deactivation functionality.</p>
        </td></tr></table><p>If EL3 is implemented:</p>
<ul>
<li>If EL3 is using AArch32, this bit is an alias of <a href="AArch32-icc_mctlr.html">ICC_MCTLR</a>.EOImode_EL1{S, NS} where S or NS corresponds to the current Security state.
</li><li>If EL3 is using AArch64, this bit is an alias of <a href="AArch64-icc_ctlr_el3.html">ICC_CTLR_EL3</a>.EOImode_EL1{S, NS} where S or NS corresponds to the current Security state.
</li></ul>
<p>If EL3 is not implemented, it is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether this bit is read-only or read/write:</p>
<ul>
<li>If this bit is read-only, an implementation can choose to make this field RAZ/WI or RAO/WI.
</li><li>If this bit is read/write, it resets to zero.
</li></ul></div><h4 id="fieldset_0-0_0">CBPR, bit [0]</h4><div class="field">
      <p>Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 interrupts:</p>
    <table class="valuetable"><tr><th>CBPR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p><a href="AArch32-icc_bpr0.html">ICC_BPR0</a> determines the preemption group for Group 0 interrupts only.</p>
<p><a href="AArch32-icc_bpr1.html">ICC_BPR1</a> determines the preemption group for Group 1 interrupts.</p></td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="AArch32-icc_bpr0.html">ICC_BPR0</a> determines the preemption group for both Group 0 and Group 1 interrupts.</p>
        </td></tr></table><p>If EL3 is implemented:</p>
<ul>
<li>If EL3 is using AArch32, this bit is an alias of <a href="AArch32-icc_mctlr.html">ICC_MCTLR</a>.CBPR_EL1{S,NS} where S or NS corresponds to the current Security state.
</li><li>If EL3 is using AArch64, this bit is an alias of <a href="AArch64-icc_ctlr_el3.html">ICC_CTLR_EL3</a>.CBPR_EL1{S,NS} where S or NS corresponds to the current Security state.
</li><li>If <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS == 0, this bit is read-only.
</li><li>If <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS == 1, this bit is read/write.
</li></ul>
<p>If EL3 is not implemented, it is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether this bit is read-only or read/write:</p>
<ul>
<li>If this bit is read-only, an implementation can choose to make this field RAZ/WI or RAO/WI.
</li><li>If this bit is read/write, it resets to zero.
</li></ul></div><div class="access_mechanisms"><h2>Accessing ICC_CTLR</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b1100</td><td>0b1100</td><td>0b100</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3.&lt;IRQ,FIQ&gt; == '11' then
        UNDEFINED;
    elsif Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; PSTATE.M != M32_Monitor &amp;&amp; SCR.&lt;IRQ,FIQ&gt; == '11' then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T12 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T12 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; ICH_HCR_EL2.TC == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; ICH_HCR.TC == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.FMO == '1' then
        R[t] = ICV_CTLR;
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.IMO == '1' then
        R[t] = ICV_CTLR;
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.FMO == '1' then
        R[t] = ICV_CTLR;
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.IMO == '1' then
        R[t] = ICV_CTLR;
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3.&lt;IRQ,FIQ&gt; == '11' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x03);
    elsif HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; PSTATE.M != M32_Monitor &amp;&amp; SCR.&lt;IRQ,FIQ&gt; == '11' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch32.TakeMonitorTrapException();
    elsif HaveEL(EL3) then
        R[t] = ICC_CTLR_NS;
    else
        R[t] = ICC_CTLR;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3.&lt;IRQ,FIQ&gt; == '11' then
        UNDEFINED;
    elsif Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; SCR.&lt;IRQ,FIQ&gt; == '11' then
        UNDEFINED;
    elsif ICC_HSRE.SRE == '0' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3.&lt;IRQ,FIQ&gt; == '11' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x03);
    elsif HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; SCR.&lt;IRQ,FIQ&gt; == '11' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch32.TakeMonitorTrapException();
    elsif HaveEL(EL3) then
        R[t] = ICC_CTLR_NS;
    else
        R[t] = ICC_CTLR;
elsif PSTATE.EL == EL3 then
    if ICC_MSRE.SRE == '0' then
        UNDEFINED;
    else
        if SCR.NS == '0' then
            R[t] = ICC_CTLR_S;
        else
            R[t] = ICC_CTLR_NS;
                </p><h4 class="assembler">MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b1100</td><td>0b1100</td><td>0b100</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3.&lt;IRQ,FIQ&gt; == '11' then
        UNDEFINED;
    elsif Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; PSTATE.M != M32_Monitor &amp;&amp; SCR.&lt;IRQ,FIQ&gt; == '11' then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T12 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T12 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; ICH_HCR_EL2.TC == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; ICH_HCR.TC == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.FMO == '1' then
        ICV_CTLR = R[t];
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.IMO == '1' then
        ICV_CTLR = R[t];
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.FMO == '1' then
        ICV_CTLR = R[t];
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.IMO == '1' then
        ICV_CTLR = R[t];
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3.&lt;IRQ,FIQ&gt; == '11' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x03);
    elsif HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; PSTATE.M != M32_Monitor &amp;&amp; SCR.&lt;IRQ,FIQ&gt; == '11' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch32.TakeMonitorTrapException();
    elsif HaveEL(EL3) then
        ICC_CTLR_NS = R[t];
    else
        ICC_CTLR = R[t];
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3.&lt;IRQ,FIQ&gt; == '11' then
        UNDEFINED;
    elsif Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; SCR.&lt;IRQ,FIQ&gt; == '11' then
        UNDEFINED;
    elsif ICC_HSRE.SRE == '0' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3.&lt;IRQ,FIQ&gt; == '11' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x03);
    elsif HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) &amp;&amp; SCR.&lt;IRQ,FIQ&gt; == '11' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch32.TakeMonitorTrapException();
    elsif HaveEL(EL3) then
        ICC_CTLR_NS = R[t];
    else
        ICC_CTLR = R[t];
elsif PSTATE.EL == EL3 then
    if ICC_MSRE.SRE == '0' then
        UNDEFINED;
    else
        if SCR.NS == '0' then
            ICC_CTLR_S = R[t];
        else
            ICC_CTLR_NS = R[t];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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